ICS93705の購入情報と機能
| この部品の機能は「DDR Phase Lock Loop Zero Delay Clock Buffer」です。 |
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製品の詳細 ( データシート PDF )

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| 部品番号 | 部品情報 | メーカー | |
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| ICS543 | PRELIMINARY INFORMATION Clock Divider and 2X Multiplier
PRELIMINARY INFORMATION
I C R O C LOC K
Description
The ICS543 is a cost effective way to produce a high quality clock output divided from a clock input. The chip accepts a clock input up to 90 MH- at 5.0 V, and by using proprietary Phase Locked Loop (PLL) techniques, produces a divide by 3, 5, 6 |
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| ICS1702 | QuickSaver Charge Controller for Nickel-Cadmium and Nickel-Metal Hydride Batteries ICS1702
QuickSaver® Charge Controller for Nickel-Cadmium and Nickel-Metal Hydride Batteries
General Description
The ICS1702 is a CMOS device designed for the intelligent charge control of either nickel-cadmium (NiCd) or nickel-metal hydride (NiMH) batteries. The controller uses a pulsed-current ch |
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| ICS9112-17 | Low Skew Output Buffer Integrated Circuit Systems, Inc.
S a t Description General a The ICS9112-17 is a high performance, low skew, low jitter .D buffer. zero delay It uses a phase lock loop (PLL) w technology to align, in both phase and frequency, the REF input with the CLKOUT signal. It is designed to distribute w spee |
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| ICS853111A | LVPECL/ECL FANOUT BUFFER
Integrated Circuit Systems, Inc.
ICS853111A
LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V, 3.3V LVPECL, ECL FANOUT BUFFER
FEATURES
10 differential 2.5V, 3.3V LVPECL , ECL outputs 2 selectable differential input pairs PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVD |
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