ICS843256の購入情報と機能
| この部品の機能は「CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER」です。 |
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製品の詳細 ( データシート PDF )

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関連検索結果
| 部品番号 | 部品情報 | メーカー | |
|---|---|---|---|
| ICS950703 | Programmable Timing Control Hub Integrated Circuit Systems, Inc.
ICS950703
Programmable Timing Control HubTM for P4TM
Recommended Application: Intel Tehema and Tehema-E Chipsets Output Features: 4 Differential CPU Clock Pairs @ 3.3V 2 - 3V MREF clocks for memory reference seeds, (separate single ended but 180 degrees out of ph |
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| ICS840004-11 | CRYSTAL-TO LVCMOS/LVTTL FREQUENCY SYNTHESIZER PRELIMINARY
Integrated Circuit Systems, Inc.
ICS840004-11
FEMTOCLOCKS™ CRYSTAL-TOLVCMOS, LVTTL FREQUENCY SYNTHESIZER
FEATURES
Four LVCMOS, LVTTL outputs, 15Ω typical output impedance Crystal oscillator interface Input frequency range: 22.4MH- to 28MH- Output frequency Range: 56MH- - 140MH- |
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| ICSSSTUAH32868A | 28-BIT CONFIGURABLE REGISTERED BUFFER
DATASHEET
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
ICSSSTUAH32868A
QERR pin (active low). The convention is even parity, i.e., valid parity is defined as an even number of ones across the DIMM-independent data inputs combined with the parity input bit. To calculate parity, all DIMM-indepen |
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| ICS844003I-01 | CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844003I-01
FEMTOCLOCKS™CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
FEATURES
Three LVDS outputs on two banks, A Bank with one LVDS pair and B Bank with 2 LVDS output pairs Using a 19.53125MH- or 25MH- crystal, the two output banks can be independentl |
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