HD74LS145の購入情報と機能

HD74ALVCH162501 18-bit Universal Bus Transceivers with 3-state Outputs ADE-205-182 (Z) Preliminary 1st. Edition December 1996 Description Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A to B data flo

HD74AC107, HD74ACT107 Dual JK Flip-Flop (with Separate Clear and Clock) Description The HD74AC107, HD74ACT107 dual JK master, slave flip-flops have a separate clock for each flip-flop. Inputs to the master section are controlled by the clock pulse. The clock pulse also regulates the state of the co

HD74LV1GT32A 2 input OR Gate , CMOS Logic Level Shifter REJ03D0120-0900 Rev.9.00 Mar 21, 2008 Description The HD74LV1GT32A is high-speed CMOS two input OR gate using silicon gate CMOS process. With CMOS low power dissipation, it provides high-speed equivalent to LS TTL series. The internal circui

19.20 20.00 Max 16 9 7.40 Max 6.30 Unit: mm 1 1.3 1.11 Max 8 0.51 Min 2.54 Min 5.06 Max 7.62 2.54 ± 0.25 0.48 ± 0.10 0.25 0.05 0° 15° Hitachi Code JEDEC EIAJ Weight (reference value) + 0.13 DP-16 Conforms Conforms 1.07 g Unit: mm 10.06 10.5 Max 16 9 5.5 1 *0.22 ± 0.05 0.20 ± 0.