DM54S188の購入情報と機能
| この部品の機能は「(32 X 8) 256-BIT TTL PROM」です。 |
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製品の詳細 ( データシート PDF )
| 部品番号 | 部品情報 | メーカー | PDF / カテゴリー |
|---|---|---|---|
| DM54S188 Data | (32 X 8) 256-BIT TTL PROM |
National Semiconductor |
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関連検索結果
| 部品番号 | 部品情報 | メーカー | |
|---|---|---|---|
| DM54LS125A | Quad TRI-STATE Buffers 54LS125A DM54LS125A DM74LS125A Quad TRI-STATE Buffers
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54LS125A DM54LS125A DM74LS125A Quad TRI-STATE Buffers
General Description
This device contains four independent gates each of which performs a non-inverting buffer function The outputs have the TRI-STATE feature When enabled the outpu |
National Semiconductor |
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| DM5476 | Dual Master-Slave J-K Flip-Flops 5476 DM5476 DM7476 Dual Master-Slave J-K Flip-Flops with Clear Preset and Complementary Outputs
June 1989
5476 DM5476 DM7476 Dual Master-Slave J-K Flip-Flops with Clear Preset and Complementary Outputs
General Description
This device contains two independent positive pulse triggered J-K flip-flop |
National Semiconductor |
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| DM54S181 | ARITHMETIC LOGIC UNIT/FUNCTION GENERATORS | National Semiconductor |
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| DM54155 | Dual 2-Line to 4-Line Decoders/Demultiplexers DM54155, DM74155 Dual 2-Line to 4-Line Decoders, Demultiplexers General Description These TTL circuits feature dual 1-line-to-4-line demultiplexers with individual strobes and common binary-address inputs in a single 16-pin package. When both sections are enabled by the strobes, the common address i |
 ETC |
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データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。 |
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