ADSP-21MSP59の購入情報と機能
| この部品の機能は「DSP Microcomputers」です。 |
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製品の詳細 ( データシート PDF )
| 部品番号 | 部品情報 | メーカー | PDF / カテゴリー |
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| ADSP-21msp59 microcomputer | DSP Microcomputers a
FEATURES 38 ns Instruction Cycle Time (26 MIPS) from 13.00 MH- Crystal ADSP-2100 Family Code and Function Compatible with New Instruction Set Enhanced for Bit Manipulation Instructions, Multiplication Instructions, Biased Rounding, and Global Interrupt Masking 2K 24 Words of On-Chip Program Memor |
Analog Devices |
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関連検索結果
| 部品番号 | 部品情報 | メーカー | |
|---|---|---|---|
| ADSP-2186LBST-133 | DSP Microcomputer | Analog Devices |
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| ADSP-21478 | SHARC Processor SHARC Processor ADSP-21477, ADSP-21478, ADSP-21479
SUMMARY
High performance 32-bit, 40-bit floating-point processor optimized for high performance audio processing
Single-instruction, multiple-data (SIMD) computational architecture
On-chip memory up to 5M bits of on-chip RAM, 4M bits of on-chip ROM |
Analog Devices |
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| ADSP-2185BST-133 | DSP Microcomputer a
FEATURES PERFORMANCE 30 ns Instruction Cycle Time 33 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle Multifunction Instructions Power-Down Mode Featuring Low CMOS Standby Power Dissi |
Analog Devices |
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| ADSP-21160N | DSP Microcomputer SUMMARY
High performance 32-bit DSP applications in audio, medical, military, graphics, imaging, and communication
Super Harvard architecture 4 independent buses for dual data fetch, instruction fetch, and nonintrusive, zero-overhead I, O
Backward compatible assembly source level compatible with cod |
Analog Devices |
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データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。 |
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