AD9525の購入情報と機能
| この部品の機能は「Low Jitter Clock Generator」です。 |
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製品の詳細 ( データシート PDF )

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関連検索結果
| 部品番号 | 部品情報 | メーカー | |
|---|---|---|---|
| AD9764 | TxDAC D/A Converter a
14-Bit, 125 MSPS TxDAC® D, A Converter
AD9764
FEATURES Member of Pin-Compatible TxDAC Product Family 125 MSPS Update Rate 14-Bit Resolution Excellent SFDR and IMD Differential Current Outputs: 2 mA to 20 mA Power Dissipation: 190 mW @ 5 V to 45 mW @ 3 V Power-Down Mode: 25 mW @ 5 V On-Chip 1.2 |
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| AD9883 | 110 MSPS Analog Interface for Flat Panel Displays a
FEATURES 110 MSPS Maximum Conversion Rate 300 MH- Analog Bandwidth 0.5 V to 1.0 V Analog Input Range 500 ps p-p PLL Clock Jitter at 110 MSPS 3.3 V Power Supply Full Sync Processing Sync Detect for ”Hot Plugging” Midscale Clamping Power-Down Mode Low Power: 500 mW Typical Composite Sync Applica |
![]() Analog Devices |
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| AD9732 | 10-Bit/ 200 MSPS D/A Converter a
D2 D3 D4 D5 D6 D7 D8 D9 D10 CLOCK TTL DRIVE LOGIC DECODERS AND DRIVERS
10-Bit, 200 MSPS D, A Converter AD9732
FUNCTIONAL BLOCK DIAGRAM
ANALOG RETURN D1 SWITCH NETWORK
FEATURES 200 MSPS Throughput Rate 3.3 V PECL Digital Input 65 dB SFDR @ 2 MH- A OUT, 200 MSPS, 54 dB @ 40 MH- A OUT, 200 MSPS Low |
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| AD9852 | CMOS 300 MHz Complete-DDS FEATURES
300 MH- internal clock rate FSK, BPSK, PSK, chirp, AM operation Dual integrated 12-bit D, A converters Ultrahigh speed comparator, 3 ps rms jitter Excellent dynamic performance
80 dB SFDR at 100 MH- (±1 MHz) AOUT 4× to 20× programmable reference clock multiplier Dual 48-bit programmable |
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