NC7SV17 データシート PDF
この部品の機能は「TinyLogic. ULP-A Single Buffer with Schmitt Trigger Input」です。
NC7SV17 Datasheet |
| 部品番号 | 部品情報 | メーカー | |
|---|---|---|---|
| NC7SV17 | TinyLogic. ULP-A Single Buffer with Schmitt Trigger Input NC7SV17 TinyLogic ULP-A Single Buffer with Schmitt Trigger Input
July 2002 Revised January 2003
NC7SV17 TinyLogic ULP-A Single Buffer with Schmitt Trigger Input
General Description
The NC7SV17 is a single buffer with Schmitt trigger input from Fairchild’s Ultra Low Power-A (ULP-A) Series of Tiny | ![]() | ![]() |
| NC7SV17L6X | TinyLogic. ULP-A Single Buffer with Schmitt Trigger Input | ![]() | ![]() |
| NC7SV17P5X | TinyLogic. ULP-A Single Buffer with Schmitt Trigger Input NC7SV17 TinyLogic ULP-A Single Buffer with Schmitt Trigger Input
July 2002 Revised January 2003
NC7SV17 TinyLogic ULP-A Single Buffer with Schmitt Trigger Input
General Description
The NC7SV17 is a single buffer with Schmitt trigger input from Fairchild’s Ultra Low Power-A (ULP-A) Series of Tiny | ![]() | ![]() |
関連検索結果
| 部品番号 | 部品情報 | メーカー | |
|---|---|---|---|
| NC7S14CW | HS Inverter with Schmitt Trigger Input | ![]() Fairchild | ![]() |
| NC7SV00P5X | TinyLogic ULP-A 2-Input NAND Gate NC7SV00 TinyLogic ULP-A 2-Input NAND Gate
June 2002 Revised May 2003
NC7SV00 TinyLogic ULP-A 2-Input NAND Gate
General Description
The NC7SV00 is a single 2-Input NAND Gate from Fairchild’s Ultra Low Power-A (ULP-A) Series of TinyLogic . ULP-A is ideal for applications that require extreme high | ![]() Fairchild | ![]() |
| NC7S14M5 | TinyLogic HS Inverter with Schmitt Trigger Input | ![]() Fairchild | ![]() |
| NC7ST02P5X | TinyLogic HST 2-Input NOR Gate NC7ST02 TinyLogic HST 2-Input NOR Gate
February 1997 Revised June 2000
NC7ST02 TinyLogic HST 2-Input NOR Gate
General Description
The NC7ST02 is a single 2-Input high performance CMOS NOR Gate, with TTL-compatible inputs. Advanced Silicon Gate CMOS fabrication assures high speed and low power circ | ![]() Fairchild | ![]() |
| NC7NZ17K8X | TinyLogic. UHS Triple Buffer with Schmitt Trigger Inputs | ![]() Fairchild | ![]() |
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