ADAU1328 データシート PDF

2 ADC, 8 DAC with PLL, 192 kHz, 24-Bit Codec ADAU1328 FEATURES PLL generated or direct master clock Low EMI design 108 dB DAC, 107 dB ADC dynamic range and SNR 94 dB THD + N Single 3.3 V supply Tolerance for 5 V logic inputs Supports 24 bits and 8 kH- to 192 kH- sample rates Differential ADC inpu

Data Sheet Low Power, 1 nV, √Hz, G ≥ 10 Stable, Railto-Rail Output Amplifier ADA4895-1, ADA4895-2 FEATURES Low wideband noise 1 nV, √H- 1.6 pA, √Hz Low 1, f noise: 2 nV, √H- at 10 H- Low distortion (SFDR): 96 dBc at 100 kHz, VOUT = 2 V p-p Low power: 3 mA per amplifier Low input offset

Data Sheet 3.1 nV, √Hz, 1 mA, 180 MHz, Rail-to-Rail Input, Output Amplifiers ADA4807-1, ADA4807-2, ADA4807-4 FEATURES Low input noise 3.1 nV, √H- at f = 100 kH- with 29 H- 1, f corner 0.7 pA, √H- at f = 100 kH- with 2 kH- 1, f corner High speed performance with dc precision 180 MHz, 3 dB ba